1. Field of the Invention
This invention relates to improvements in voltage gain stages, and more particularly to improvements in temperature compensated voltage gain stages.
2. Relevant Background
Many applications exist for fast and simple differential pair gain stages, particularly for high speed applications. A typical gain stage 10 is shown in FIG. 1. The gain stage 10 includes a differential transistor pair that includes NPN transistors 12 and 14 to the respective gates of which a differential input voltage V.sub.IN is applied. Load resistors 16 and 18 are connected between the respective collectors of transistors 12 and 14 and a supply voltage, V.sub.CC. The resistors 16 and 18 have a value of R.sub.2.
The emitters of the transistors 12 and 14 are connected by current sources 20 and 22, respectively, to a referenced potential, or ground. A pair of resistors, each of value R.sub.1, 24 and 26 are connected between the emitters of the transistors 12 and 14. (Two resistors are shown for ease of calculation; of course, a single resistor of value 2R.sub.1 may be substituted therefor.) The circuit output is obtained at the collectors of the transistors 12 and 14 as differential output voltages, V.sub.0, on output terminals 28 and 30.
The voltage gain of the circuit is ##EQU1##
Since V.sub.T has a positive temperature coefficient, the overall gain of the circuit 10 is temperature dependent. One way that has been proposed to reduce the temperature dependence problem is to use a PTAT tail current source. One characteristic of the PTAT tail current source is that the current I.sub.T =KV.sub.T. However, variations in the tail current that may be provided by the PTAT tail current source may change the quiescent collector voltage of the transistors 12 and 14. As a result, variations in DC voltage drop across the load resistors R.sub.2 can be troublesome if high gain is desirable.
Another way that such voltage gain stages have been temperature compensated is to attempt to provide circuitry to cancel the V.sub.T /I.sub.T term in the gain equation set forth above. One way that has been proposed to cancel this term is by providing a cross-coupled circuit 40, as shown in FIG. 2. The circuit 40 is constructed similarly to the circuit 10 shown in FIG. 1, with corresponding parts similarly numbered, except that a pair of additional bipolar transistors 32 and 34 are provided. The transistors 32 and 34 are cross coupled, with the base of each being connected to the collector of the other. The cross-quad connectors 32 and 34 provide a transconductance ##EQU2##
term in the denominator of the gain equation. This cancels the g.sub.m of transistors 12 and 14.
However, the circuit 40 has several drawbacks. Since the devices are cascaded, head-room is reduced. In addition, the dynamic range is not just limited by currents through the transistors, but is also limited by the transistors 32 and 34 as they are forward biased as the input signal increases differentially. Finally, the reactive component of the input impedance looking into the bases of input transistors 12 and 14 can be negative. Consequently, the circuit can become unstable, if it is not carefully designed.